ISCA Tutorial 2012

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June 10th, 2012 at 39th ISCA in Portland, OR

Tutorial Slides

Thanks for all attendees to make MARSS tutorial at ISCA a great success. Here are the slides of this tutorial.


Single and multicore processors implementing the x86 instruction set architecture (ISA) are deployed within many computing platforms today, starting from high-end servers to desktops and ultimately down to mobile devices (using the Intel Atom and its announced successors), including potential new products that target the smart phone market segment and beyond. The one clear advantage of using the x86 processors in the full range of the product spectrum is to facilitate the rapid deployment of the wide variety of x86 application binaries. It is thus important to have a full system simulation tool that incorporates realistic simulation models for other systems level components such as the chipset, DRAM, network interface cards and peripheral devices in addition to accurate simulation models for single and multicore processors implementing the x86 ISA. Such a tool is useful for evaluating and developing products that will use current and emerging single and multicore x86 chips. We have developed an open source full system simulation tool, called MARSS – Micro Architectural and System Simulator, to meet this critical need. The current public release of MARSS supports single core and multi-core X86 platforms, running the Linux OS. Unmodified X86 binaries can be simulated or emulated in MARSS. MARSS is currently being extended to support the ARM ISA in an Android environment. MARSS extends the widely used QEMU framework – a full system emulator that supports multiple ISA, with cycle accurate simulation framework based on PTLsim. MARSS provides a modular framework to implement Core and Cache models like Out-Of-Order core, Atom like In-Order core, Write-back/Write-through caches, MESI and MOESI coherent Caches, Bus and Switch interconnects. This modular framework also allows users to easily integrate other open-source or proprietary tools, for example DRAMSim2 (detailed DRAM simulator) uses MARSS as front-end to generate traffic to DRAM model.

MARSS has attracted not only the academic researchers but also industrial researchers from Intel, Rambus, Cray Systems and others as viable open-source alternative to many existing proprietary and closed source tools. Researchers from Rambus have evaluated MARSS's performance with real hardware and are working towards improving its co-relation with hardware. Intel research labs have utilized MARSS framework to develop multicore memory tracing tool and they are working to integrate it with x86 Android Emulator.

Tutorial Program

This full-day tutorial focuses on the MARSS simulation environment and is organized into the following sections:

Time Title Details/Demos
09:00 - 10:00 Introduction to MARSS Overview of MARSS architecture and quick demo of how to get started with MARSS
10:00 - 10:30 Coffee Break
10:30 - 12:00 Internal Components of MARSS
  • Details on Full System Simulation Framework
  • Internals of Out-Of-Order and Atom Core Modules
  • Internals of various Memory Hierarchy Modules
12:00 - 13:00 Lunch Break
13:00 - 14:30 Internal Components of MARSS (Cont.)
  • Statistics Collection
  • Building Simulated Machines
14:30 - 15:30 Industrial Experience with MARSS
  • Rambus : Validating MARSS performance with real platforms
  • Intel  : Developing Multicore Memory Tracing capabilities in MARSS and integrating MARSS to x86 based Android Emulator
15:30 - 16:00 Coffee Break
16:00 - 16:30 DRAMSim2 - Detail DRAM Simulator Leveraging MARSS Framework for Detailed DRAM Simulations with Full-System Components
16:30 - 17:00 Q & A Closing Remarks and Q & A Session
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